EC2354 VLSI DESIGN 2 MARKS WITH ANSWERS PDF
SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.
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List the different types of shifter. What is Channel-length modulation?
An approach to fault analysis is known as fault sampling. It can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level.
Which factors dominates the performance of a programmable shifter? That makes latch based design more efficient. Write the applications of transmission gate? FPGAs can be used to implement a logic circuit with more than 20, gates whereas a Qith can implement circuits of upto about 20, equivalent gates.
What is fault grading? When a bridging fault occurs, for some combination of input conditions a measurable DC IDD will flow. What is dynamic hazard? What are the different operating regions foe an MOS transistor?
ECVLSI DESIGN 2 MARK QUESTIONS & ANSWERS | Md Ashwaqamer –
The increasing complexity of boards and the movement to technologies like multichip modules and surface-mount technologies resulted in system designers agreeing on a unified scan-based methodology for testing chips at the board.
Latch up is a condition in which the parasitic components give rise to the ddesign of low resistance conducting paths between VDD and VSS with disastrous results. What is known as test data register? The effective length of the conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel. Contact cut definition 5.
All 6th Semester ECE Question Paper and 2 Marks with Answers – Kiruba Edition
Final stable state depends on the order in which the state variable changes then that race condition is called critical race and it is harmful. Click here maeks sign up. It is an analytical method used to estimate the RC delay in a network. What is clock skew? Hold time is always measured from the rising clock edge to a point after the clock edge.
A fundamental difficulty with dynamic circuits is a loss of noise immunity and a serious timing restriction on the inputs of the gate. What are the uses of stick diagram?
What is the TAP controller? The Device that conduct with zero gate bias.
Performance increase comes at the cost of area. A field programmable gate array FPGA is a programmable logic answees that supports implementation of relatively large logic circuits.
What is the fundamental goal in Device modeling?
A device connected so as to pull the output voltage to v,si upper supply voltage usually VDD is called pull up device. What is pull down device? The major advantages of pipelining are to reduce glitch in complex logic networks and getting lower energy due to operand isolation.
Green — n-diffusion Red- polysilicon Blue —metal Yellow- implant Black-contact areas.
The effective length of the conductive channel is actually modulated by desigj applied voltage VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel. Setup time is a requirement that the data has to be stable before the clock edge and hold time is a requirement that the data has to be stable after the clock edge.
What are the scan-based test techniques? Transistors with Channel length less than 3- 5 microns are termed as Short channel devices.